199 search results - page 30 / 40 » Switching Activity Minimization in Combinational Logic Desig... |
WECWIS
2002
IEEE
15 years 4 months ago
2002
IEEE
In the web context, it is difficult to disentangle presentation from process logic, and sometimes even data is not separate from the presentation. Consequently, it becomes to de...
GLVLSI
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...
DAC
2006
ACM
15 years 5 months ago
2006
ACM
Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require ...
109
Voted
MJ
2007
14 years 11 months ago
2007
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
ATS
2000
IEEE
15 years 4 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...