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ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
15 years 5 months ago
Thermal-induced leakage power optimization by redundant resource allocation
Traditionally, at early design stages, leakage power is associated with the number of transistors in a design. Hence, intuitively an implementation with minimum resource usage wou...
Min Ni, Seda Ogrenci Memik
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
15 years 5 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
BMCBI
2008
103views more  BMCBI 2008»
14 years 11 months ago
Detection of protein catalytic residues at high precision using local network properties
Background: Identifying the active site of an enzyme is a crucial step in functional studies. While protein sequences and structures can be experimentally characterized, determini...
Patrick Slama, Ioannis Filippis, Michael Lappe
ISLPED
2005
ACM
136views Hardware» more  ISLPED 2005»
15 years 5 months ago
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy
Concerns about the reliability of real-time embedded systems that employ dynamic voltage scaling has recently been highlighted [1,2,3], focusing on transient-fault-tolerance techn...
Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Ha...
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
15 years 5 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba