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ITC
1999
IEEE
78views Hardware» more  ITC 1999»
15 years 3 months ago
Minimized power consumption for scan-based BIST
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
Stefan Gerstendörfer, Hans-Joachim Wunderlich
GLVLSI
2003
IEEE
171views VLSI» more  GLVLSI 2003»
15 years 4 months ago
Combining wire swapping and spacing for low-power deep-submicron buses
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...
Enrico Macii, Massimo Poncino, Sabino Salerno
DAC
2005
ACM
16 years 17 days ago
A novel synthesis approach for active leakage power reduction using dynamic supply gating
: Due to exponential increase in subthreshold leakage with technology scaling and temperature increase, leakage power is becoming a major fraction of total power in the active mode...
Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hami...
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KDD
2009
ACM
180views Data Mining» more  KDD 2009»
16 years 4 days ago
Using graph-based metrics with empirical risk minimization to speed up active learning on networked data
Active and semi-supervised learning are important techniques when labeled data are scarce. Recently a method was suggested for combining active learning with a semi-supervised lea...
Sofus A. Macskassy
DATE
2005
IEEE
121views Hardware» more  DATE 2005»
15 years 5 months ago
Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
Paul Zuber, Armin Windschiegl, Raúl Medina ...