462 search results - page 17 / 93 » Symbolic Bounded Synthesis |
112
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DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
15 years 6 months ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper proposes a novel architecture synthesis algorithm for single-loop single-bit ∆Σ modulators. We defined a generic modulator architecture and derived its noise and si...
103
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EURODAC
1995
IEEE
15 years 5 months ago
1995
IEEE
Computing equivalence classes for FSMs has several applications to synthesis and veri cation problems. Symbolic traversal techniques are applicable to medium-small circuits. This ...
112
Voted
CORR
2011
Springer
14 years 5 months ago
2011
Springer
Consider a linear [n, k, d]q code C. We say that that i-th coordinate of C has locality r, if the value at this coordinate can be recovered from accessing some other r coordinates...
100
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RTCSA
1998
IEEE
15 years 6 months ago
1998
IEEE
In this paper, we propose a protocol synthesis method based on a partial order model (called event structures) for the class of context-free processes. First, we assign a unique n...