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» Symbolic Execution of Behavioral Requirements
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88
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HPCA
2005
IEEE
15 years 11 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
15 years 4 months ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
87
Voted
ISSTA
2010
ACM
15 years 2 months ago
Testing system virtual machines
Virtual machines offer the ability to partition the resources of a physical system and to create isolated execution environments. The development of virtual machines is a very ch...
Lorenzo Martignoni, Roberto Paleari, Giampaolo Fre...
120
Voted
DAC
2010
ACM
15 years 2 months ago
Scalable specification mining for verification and diagnosis
Effective system verification requires good specifications. The lack of sufficient specifications can lead to misses of critical bugs, design re-spins, and time-to-market slips. I...
Wenchao Li, Alessandro Forin, Sanjit A. Seshia
89
Voted
CODES
2006
IEEE
15 years 5 months ago
Integrated analysis of communicating tasks in MPSoCs
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
Simon Schliecker, Matthias Ivers, Rolf Ernst