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DAC
2005
ACM
14 years 7 months ago
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration
Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We ...
Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. D...
IPPS
1998
IEEE
13 years 10 months ago
Processor Lower Bound Formulas for Array Computations and Parametric Diophantine Systems
Using a directed acyclic graph (dag) model of algorithms, we solve a problem related to precedenceconstrained multiprocessor schedules for array computations: Given a sequence of ...
Peter R. Cappello, Ömer Egecioglu
FCCM
2009
IEEE
134views VLSI» more  FCCM 2009»
13 years 10 months ago
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Gh...
JSSPP
2009
Springer
14 years 23 days ago
Limits of Work-Stealing Scheduling
The number of applications with many parallel cooperating processes is steadily increasing, and developing efficient runtimes for their execution is an important task. Several fram...
Zeljko Vrba, Håvard Espeland, Pål Halv...
ICALP
2011
Springer
12 years 9 months ago
Clustering with Local Restrictions
We study a family of graph clustering problems where each cluster has to satisfy a certain local requirement. Formally, let µ be a function on the subsets of vertices of a graph G...
Daniel Lokshtanov, Dániel Marx