50 search results - page 2 / 10 » Synchronization Processor Synthesis for Latency Insensitive ... |
TCAD
2008
13 years 6 months ago
2008
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
ENTCS
2006
13 years 6 months ago
2006
Latency insensitive protocols (LIPs) have been proposed as a viable means to connect synchronous IP blocks via long interconnects in a system-on-chip. The reason why one needs to ...
DSD
2009
IEEE
13 years 4 months ago
2009
IEEE
Abstract--The implementation of an efficient result forwarding unit for asynchronous processors faces the problem of the inherent lack of synchronisation between result producer an...
CAV
1999
Springer
13 years 10 months ago
1999
Springer
The theory of latency insensitive design is presented as the foundation of a new correct by construction methodology to design very large digital systems by assembling blocks of In...
NOCS
2008
IEEE
14 years 19 days ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...