50 search results - page 4 / 10 » Synchronization Processor Synthesis for Latency Insensitive ... |
STORAGESS
2006
ACM
15 years 3 months ago
2006
ACM
This paper argues that the network latency due to synchronous replication is no longer tolerable in scenarios where businesses are required by regulation to separate their seconda...
IISWC
2008
IEEE
15 years 4 months ago
2008
IEEE
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
TCAD
2008
14 years 9 months ago
2008
This paper describes an integer-linear-programming (ILP)-based system called Custom Hardware Instruction Processor Synthesis (CHIPS) that identifies custom instructions for critica...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
SAMOS
2004
Springer
15 years 2 months ago
2004
Springer
This paper presents a novel micro-architecture for high-performance and low-power DSPs. The underlying Synchronous Transfer Architecture (STA) fills the gap between SIMD-DSPs and ...