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IEEEPACT
2009
IEEE
15 years 11 months ago
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
Qingda Lu, Christophe Alias, Uday Bondhugula, Thom...
136
Voted
GG
2004
Springer
15 years 10 months ago
Fundamental Theory for Typed Attributed Graph Transformation
The concept of typed attributed graph transformation is most significant for modeling and meta modeling in software engineering and visual languages, but up to now there is no ade...
Hartmut Ehrig, Ulrike Prange, Gabriele Taentzer
IEEEPACT
2009
IEEE
15 years 11 months ago
Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
Basilio B. Fraguela, Yevgen Voronenko, Markus P&uu...
DSD
2009
IEEE
147views Hardware» more  DSD 2009»
15 years 8 months ago
A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computat...
Abdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu
TAICPART
2010
IEEE
133views Education» more  TAICPART 2010»
15 years 3 months ago
Localizing Defects in Multithreaded Programs by Mining Dynamic Call Graphs
Abstract. Writing multithreaded software for multicore computers confronts many developers with the difficulty of finding parallel programming errors. In the past, most parallel d...
Frank Eichinger, Victor Pankratius, Philipp W. L. ...