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» Synchronization Transformations for Parallel Computing
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135
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IPPS
2009
IEEE
15 years 9 months ago
Using hardware transactional memory for data race detection
Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
Shantanu Gupta, Florin Sultan, Srihari Cadambi, Fr...
IPPS
2009
IEEE
15 years 9 months ago
Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
IPPS
2003
IEEE
15 years 7 months ago
ECO: An Empirical-Based Compilation and Optimization System
In this paper, we describe a compilation system that automates much of the process of performance tuning that is currently done manually by application programmers interested in h...
Nastaran Baradaran, Jacqueline Chame, Chun Chen, P...
113
Voted
IPPS
1999
IEEE
15 years 6 months ago
PM-PVM: A Portable Multithreaded PVM
PM-PVM is a portable implementation of PVM designed to work on SMP architectures supporting multithreading. PM-PVM portability is achieved through the implementation of the PVM fu...
Claudio M. P. Santos, Júlio S. Aude
103
Voted
IPPS
1998
IEEE
15 years 6 months ago
Performance and Experience with LAPI - a New High-Performance Communication Library for the IBM RS/6000 SP
LAPI is a low-level, high-performance communication interface available on the IBM RS/6000 SP system. It provides an activemessage-like interface along with remote memory copy and...
Gautam Shah, Jarek Nieplocha, Jamshed H. Mirza, Ch...