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» Synchronization and Communication in the T3E Multiprocessor
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ASPLOS
1996
ACM
15 years 4 months ago
Synchronization and Communication in the T3E Multiprocessor
This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have l...
Steven L. Scott
IPPS
1999
IEEE
15 years 4 months ago
Portable Parallel Programming for the Dynamic Load Balancing of Unstructured Grid Applications
The ability to dynamically adapt an unstructured grid (or mesh) is a powerful tool for solving computational problems with evolving physical features; however, an efficient parall...
Rupak Biswas, Leonid Oliker, Sajal K. Das, Daniel ...
TVLSI
2010
14 years 7 months ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas
DAC
2008
ACM
16 years 1 months ago
Latency and bandwidth efficient communication through system customization for embedded multiprocessors
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
Chenjie Yu, Peter Petrov
ISVLSI
2006
IEEE
115views VLSI» more  ISVLSI 2006»
15 years 6 months ago
Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems
This paper investigates the performance and power dissipation of Globally Asynchronous Locally Synchronous (GALS) multi-processor systems. We show that communication loops are a s...
Zhiyi Yu, Bevan M. Baas