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DATE
2004
IEEE
126views Hardware» more  DATE 2004»
15 years 8 months ago
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
Montek Singh, Michael Theobald
EPEW
2010
Springer
15 years 5 months ago
Composing Systems While Preserving Probabilities
Abstract. Restricting the power of the schedulers that resolve the nondeterminism in probabilistic concurrent systems has recently drawn the attention of the research community. Th...
Sonja Georgievska, Suzana Andova
ENTCS
2007
101views more  ENTCS 2007»
15 years 4 months ago
Systems Modelling via Resources and Processes: Philosophy, Calculus, Semantics, and Logic
We describe a programme of research in resource semantics, concurrency theory, bunched logic, and stochastic processes, as applied to mathematical systems modelling. Motivated by ...
David J. Pym, Chris M. N. Tofts
TCAD
2008
103views more  TCAD 2008»
15 years 4 months ago
Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
Rebecca L. Collins, Luca P. Carloni
VTC
2007
IEEE
15 years 10 months ago
A Novel Timing and Frequency Offset Estimation Scheme for OFDM Systems
— A novel structure of training symbol is proposed for orthogonal frequency division multiplexing (OFDM) systems. With the proposed training symbol, which has repeated sample blo...
Shun-Sheng Wang, Chih-Peng Li, Chin-Liang Wang