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IJON
2000
78views more  IJON 2000»
15 years 4 months ago
Model-free detection of synchrony in neuronal spike trains, with an application to primate somatosensory cortex
Synchronized neuronal ring has been reported in many neural systems and may play a role in the representation of sensory stimuli and the modi cation of sensory representations by ...
Arup Roy, Peter N. Steinmetz, Ken O. Johnson, Erns...
FPL
2010
Springer
134views Hardware» more  FPL 2010»
15 years 2 months ago
GPU Versus FPGA for High Productivity Computing
Heterogeneous or co-processor architectures are becoming an important component of high productivity computing systems (HPCS). In this work the performance of a GPU based HPCS is c...
David Huw Jones, Adam Powell, Christos-Savvas Boug...
TVLSI
2010
14 years 11 months ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas
ASPLOS
2011
ACM
14 years 8 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
DAC
2009
ACM
16 years 5 months ago
Context-sensitive timing analysis of Esterel programs
Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty, Abh...