Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
Interest in asynchronous circuit design is increasing due to its promise of efficient designs. The quiescent nature of asynchronous circuits allows them to remain in a stable stat...
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
The study of synchronization has received much attention in a variety of applications, ranging from coordinating sensors in wireless networks to models of fireflies flashing in...
We consider the fundamental problem of waking up n processors sharing a multiple access channel. We assume the weakest model of synchronization, the locally synchronous model, in ...
Gianluca De Marco, Marco Pellegrini, Giovanni Sbur...