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» Synchronization of periodic clocks
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DAC
1994
ACM
15 years 6 months ago
Clock Grouping: A Low Cost DFT Methodology for Delay Testing
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
Wen-Chang Fang, Sandeep K. Gupta
TCAD
2002
146views more  TCAD 2002»
15 years 1 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
15 years 8 months ago
Integrated placement and skew optimization for rotary clocking
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C....
WSNA
2003
ACM
15 years 7 months ago
Lightweight time synchronization for sensor networks
This paper presents lightweight tree-based synchronization (LTS) methods for sensor networks. First, a single-hop, pair-wise synchronization scheme is analyzed. This scheme requir...
Jana van Greunen, Jan M. Rabaey
ISLPED
1997
ACM
81views Hardware» more  ISLPED 1997»
15 years 6 months ago
A method of redundant clocking detection and power reduction at RT level design
This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clocki...
Mitsuhisa Ohnishi, Akihisa Yamada, Hiroaki Noda, T...