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» Synchronization of periodic clocks
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ISCA
2005
IEEE
166views Hardware» more  ISCA 2005»
15 years 5 months ago
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
Emil Talpes, Diana Marculescu
ITC
1998
IEEE
94views Hardware» more  ITC 1998»
15 years 4 months ago
A method of serial data jitter analysis using one-shot time interval measurements
A method for measuring inter-symbol interference, duty cycle distortion, random jitter and periodic jitter is described. The Blackman-Tukey method of signal analysis is used. This...
Jan B. Wilstrup
ASPDAC
2009
ACM
127views Hardware» more  ASPDAC 2009»
15 years 6 months ago
Timing driven power gating in high-level synthesis
- The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock ...
Shih-Hsu Huang, Chun-Hua Cheng
CHI
2008
ACM
16 years 7 days ago
Temporal trajectories in shared interactive narratives
Temporal trajectories can represent the complex mappings between story time and clock time that are to be found in shared interactive narratives such as computer games and interac...
Steve Benford, Gabriella Giannachi
FMICS
2008
Springer
15 years 1 months ago
Extending Structural Test Coverage Criteria for Lustre Programs with Multi-clock Operators
Lustre is a formal synchronous declarative language widely used for modeling and specifying safety-critical applications in the elds of avionics, transportation or energy productio...
Virginia Papailiopoulou, Laya Madani, Lydie du Bou...