651 search results - page 77 / 131 » Synchronization of periodic clocks |
ICCAD
2003
IEEE
15 years 8 months ago
2003
IEEE
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
ISPD
2006
ACM
15 years 5 months ago
2006
ACM
The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly ...
ICONS
2009
IEEE
15 years 6 months ago
2009
IEEE
The power saving is one of the important issue in the embedded systems. To reduce the consumption of the microprocessor of such a system, a way is to power down it when it is inac...
DATE
2004
IEEE
15 years 3 months ago
2004
IEEE
In this paper, we propose a simple technique for estimating the standard deviation of a Gaussian random jitter component in a multi-gigahertz signal. This method may utilize exist...
ISVLSI
2005
IEEE
15 years 5 months ago
2005
IEEE
The clock period in conventional pipeline scheme is proportional to the maximum delay while in hybrid wave-pipelining it is proportional to the maximum delay difference. An 8×8-b...