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ACSD
2005
IEEE
71views Hardware» more  ACSD 2005»
15 years 5 months ago
Maximal Causality Analysis
Perfectly synchronous systems immediately react to the inputs of their environment, which may lead to so-called causality cycles between actions and their trigger conditions. Algo...
Klaus Schneider, Jens Brandt, Tobias Schüle, ...
ISMVL
2005
IEEE
86views Hardware» more  ISMVL 2005»
15 years 4 months ago
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders
A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in Low-Density Parity-Check (LDPC) decoders, where high-throughput ...
Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu
PATMOS
2005
Springer
15 years 4 months ago
Enhanced GALS Techniques for Datapath Applications
Abstract. Based on a previously reported request driven technique for Globally-Asynchronous Locally-Synchronous (GALS) circuits this paper presents two significant enhancements. Fi...
Eckhard Grass, Frank Winkler, Milos Krstic, Alexan...
CHARME
2001
Springer
117views Hardware» more  CHARME 2001»
15 years 3 months ago
A Higher-Level Language for Hardware Synthesis
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
Richard Sharp, Alan Mycroft
ARVLSI
1999
IEEE
94views VLSI» more  ARVLSI 1999»
15 years 3 months ago
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
Ayoob E. Dooply, Kenneth Y. Yun