95 search results - page 9 / 19 » Synchronous Interlocked Pipelines |
102
click to vote
ASPLOS
1996
ACM
15 years 4 months ago
1996
ACM
This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have l...
118
click to vote
WWW
2005
ACM
16 years 1 months ago
2005
ACM
Design of high performance Web servers has become a recent research thrust to meet the increasing demand of networkbased services. In this paper, we propose a new Web server archi...
123
Voted
MICRO
2010
IEEE
14 years 10 months ago
2010
IEEE
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
111
Voted
CVPR
2007
IEEE
16 years 2 months ago
2007
IEEE
This paper presents our progress on OpenVL - a novel software architecture to address efficiency through facilitating hardware acceleration, reusability and scalability for comput...
104
Voted
DAC
2004
ACM
16 years 1 months ago
2004
ACM
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...