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ATS
2004
IEEE
97views Hardware» more  ATS 2004»
15 years 1 months ago
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin N...
ARCS
2006
Springer
15 years 1 months ago
Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors
Abstract. This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results usin...
Nabil Hasasneh, Ian Bell, Chris R. Jesshope
ATVA
2006
Springer
160views Hardware» more  ATVA 2006»
15 years 1 months ago
Monotonic Set-Extended Prefix Rewriting and Verification of Recursive Ping-Pong Protocols
Ping-pong protocols with recursive definitions of agents, but without any active intruder, are a Turing powerful model. We show that under the environment sensitive semantics (i.e....
Giorgio Delzanno, Javier Esparza, Jirí Srba
CSCWD
2006
Springer
15 years 1 months ago
Using Isolation Spheres for Cooperative Processes Correctness
Managing cooperation in Business Processes still represents a challenge because of several problems. Concurrent access to common data, coherence of the results, organisation and c...
Adnene Guabtni, François Charoy, Claude God...
EDBTW
2006
Springer
15 years 1 months ago
Conflict Resolution in Updates Through XML Views
Abstract. In this paper, we focus on B2B scenarios where XML views are extracted from relational databases and sent over the Web to another application that edits them and sends th...
André Prisco Vargas, Vanessa P. Braganholo,...