Sciweavers

366 search results - page 41 / 74
» Synthesis: Words and Traces
Sort
View
IESS
2007
Springer
110views Hardware» more  IESS 2007»
15 years 3 months ago
Run-Time efficient Feasibility Analysis of Uni-Processor Systems with Static Priorities
: The performance of feasibility tests is crucial in many applications. When using feasibility tests online only a limited amount of analysis time is available. Run-time efficiency...
Karsten Albers, Frank Bodmann, Frank Slomka
DDECS
2006
IEEE
79views Hardware» more  DDECS 2006»
15 years 3 months ago
Multiple-Vector Column-Matching BIST Design Method
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
Petr Fiser, Hana Kubatova
ICCS
2005
Springer
15 years 3 months ago
A Logarithmic Time Method for Two's Complementation
This paper proposes an innovative algorithm to find the two’s complement of a binary number. The proposed method works in logarithmic time (O(logN)) instead of the worst case li...
Jung-Yup Kang, Jean-Luc Gaudiot
FPL
2006
Springer
223views Hardware» more  FPL 2006»
15 years 1 months ago
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
Carlos Morra, M. Sackmann, Sunil Shukla, Jürg...
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
15 years 1 months ago
Timing optimization by bit-level arithmetic transformations
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De M...