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FPL
2005
Springer
98views Hardware» more  FPL 2005»
15 years 3 months ago
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs
Modern heterogeneous FPGAs contain “hard” specificpurpose structures such as blocks of memory and multipliers in addition to the completely flexible “soft” programmable ...
Peter Jamieson, Jonathan Rose
CATA
2009
14 years 11 months ago
Built-in Self-Test for Memory Resources in Virtex-4 Field Programmable Gate Arrays
ABSTRACT: We present a Built-In Self-Test (BIST) approach for programmable embedded memories in Xilinx Virtex-4 Field Programmable Gate Arrays (FPGAs). The target resources are the...
Brooks R. Garrison, Daniel T. Milton, Charles E. S...
FPL
2004
Springer
112views Hardware» more  FPL 2004»
15 years 3 months ago
Storage Allocation for Diverse FPGA Memory Specifications
A previous study [1] demonstrates the advantages of replacing registers by FPGA embedded memories during the storage allocation phase of High-Level Synthesis. The trend in new FPGA...
Dalia Dagher, Iyad Ouaiss
SAMOS
2005
Springer
15 years 3 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&...
DATE
2009
IEEE
144views Hardware» more  DATE 2009»
15 years 4 months ago
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing
—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of...
Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Ake...