19 search results - page 4 / 4 » Synthesis for Logical Initializability of Synchronous Finite... |
DFT
1998
IEEE
13 years 10 months ago
1998
IEEE
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
DSD
2006
IEEE
13 years 8 months ago
2006
IEEE
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
IOLTS
2009
IEEE
14 years 27 days ago
2009
IEEE
— The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault toleran...
ASE
2005
13 years 6 months ago
2005
Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...