Sciweavers

16 search results - page 2 / 4
» Synthesis of Asynchronous Circuits Using Early Data Validity
Sort
View
VLSID
1999
IEEE
91views VLSI» more  VLSID 1999»
13 years 10 months ago
Timed Circuit Synthesis Using Implicit Methods
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...
Robert Thacker, Wendy Belluomini, Chris J. Myers
VLSI
2005
Springer
13 years 11 months ago
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
Bertrand Folco, Vivian Brégier, Laurent Fes...
ACSD
2009
IEEE
106views Hardware» more  ACSD 2009»
13 years 4 months ago
Teak: A Token-Flow Implementation for the Balsa Language
This paper describes a new target component set and synthesis scheme for the Balsa asynchronous hardware description language. This new scheme removes the reliance on precise hands...
Andrew Bardsley, Luis A. Tarazona, Doug A. Edwards
ISMVL
2003
IEEE
101views Hardware» more  ISMVL 2003»
13 years 11 months ago
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic
A new asynchronous data transfer scheme using multiple-valued 2-color 1-phase coding, called a bidirectional data transfer scheme, is proposed for a highperformance and low-power ...
Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kame...
ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
13 years 11 months ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu