The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...
This paper describes a new target component set and synthesis scheme for the Balsa asynchronous hardware description language. This new scheme removes the reliance on precise hands...
Andrew Bardsley, Luis A. Tarazona, Doug A. Edwards
A new asynchronous data transfer scheme using multiple-valued 2-color 1-phase coding, called a bidirectional data transfer scheme, is proposed for a highperformance and low-power ...
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...