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ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
15 years 5 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
15 years 7 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
DAC
2003
ACM
16 years 3 months ago
Using estimates from behavioral synthesis tools in compiler-directed design space exploration
This paper considers the role of performance and area estimates from behavioral synthesis in design space exploration. We have developed a compilation system that automatically ma...
Byoungro So, Pedro C. Diniz, Mary W. Hall
SPAA
2009
ACM
15 years 11 months ago
At-most-once semantics in asynchronous shared memory
Abstract. At-most-once semantics is one of the standard models for object access in decentralized systems. Accessing an object, such as altering the state of the object by means of...
Sotiris Kentros, Aggelos Kiayias, Nicolas C. Nicol...
CONCUR
2006
Springer
15 years 6 months ago
Minimization, Learning, and Conformance Testing of Boolean Programs
Boolean programs with recursion are convenient abstractions of sequential imperative programs, and can be represented as recursive state machines (RSMs) or pushdown automata. Motiv...
Viraj Kumar, P. Madhusudan, Mahesh Viswanathan