82 search results - page 13 / 17 » Synthesis of High Performance Low Power Dynamic CMOS Circuit... |
ISLPED
2010
ACM
14 years 9 months ago
2010
ACM
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
ICCD
2001
IEEE
15 years 6 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
ISQED
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
ASYNC
2005
IEEE
15 years 3 months ago
2005
IEEE
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...