Sciweavers

127 search results - page 11 / 26
» Synthesis of Operation-Centric Hardware Descriptions
Sort
View
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
15 years 1 months ago
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
CCL
1994
Springer
15 years 1 months ago
Application of Constraint Logic Programming for VLSI CAD Tools
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...
Renate Beckmann, Ulrich Bieker, Ingolf Markhof
ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
15 years 2 months ago
Efficient Simulation of Synthesis-Oriented System Level Designs
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu
DATE
2006
IEEE
86views Hardware» more  DATE 2006»
15 years 3 months ago
Synthesis of system verilog assertions
In recent years, Assertion-Based Verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip(SOC) designs. The System Verilog langua...
Sayantan Das, Rizi Mohanty, Pallab Dasgupta, P. P....
DATE
2003
IEEE
122views Hardware» more  DATE 2003»
15 years 2 months ago
Synthesis of Complex Control Structures from Behavioral SystemC Models
In this paper we present the results of a set of experiments we conducted in order to evaluate the viability of the behavioral synthesis, relying on the tools available at the mom...
Francesco Bruschi, Fabrizio Ferrandi