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DSD
2002
IEEE
103views Hardware» more  DSD 2002»
15 years 2 months ago
On the Fundamental Design Gap in Terabit per Second Packet Switching
We discuss the gap we experience in an industrial design path of high-speed packet switches. As bandwidth demand exceeds progress in CMOS technology, system architects are forced ...
M. Verhappen, P. H. A. van der Putten, Jeroen Voet...
ICCD
2005
IEEE
165views Hardware» more  ICCD 2005»
15 years 6 months ago
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
Ernst Martin Witte, Anupam Chattopadhyay, Oliver S...
ICCAD
2001
IEEE
143views Hardware» more  ICCAD 2001»
15 years 6 months ago
Transient Power Management Through High Level Synthesis
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...
Vijay Raghunathan, Srivaths Ravi, Anand Raghunatha...
DAC
1999
ACM
15 years 1 months ago
Common-Case Computation: A High-Level Technique for Power and Performance Optimization
This paper presents a design methodology, called common-case computation (CCC), and new design automation algorithms for optimizing power consumption or performance. The proposed ...
Ganesh Lakshminarayana, Anand Raghunathan, Kamal S...
DFT
2007
IEEE
123views VLSI» more  DFT 2007»
15 years 3 months ago
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
Martin Straka, Jiri Tobola, Zdenek Kotásek