Sciweavers

127 search results - page 19 / 26
» Synthesis of Operation-Centric Hardware Descriptions
Sort
View
ICCAD
2008
IEEE
127views Hardware» more  ICCAD 2008»
15 years 6 months ago
System-level power estimation using an on-chip bus performance monitoring unit
In this paper we propose an on-chip bus PMU which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity in...
Youngjin Cho, Younghyun Kim, Sangyoung Park, Naehy...
FCCM
2009
IEEE
192views VLSI» more  FCCM 2009»
15 years 4 months ago
FPGA Floating Point Datapath Compiler
This paper will describe the architecture of a compiler which will convert an untimed C description of a set of floating point expressions into a synthesizable datapath optimized ...
Martin Langhammer, Tom VanCourt
DAC
2006
ACM
15 years 10 months ago
Behavior and communication co-optimization for systems with sequential communication media
In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writi...
Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zh...
FCCM
2002
IEEE
146views VLSI» more  FCCM 2002»
15 years 2 months ago
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. Thes...
Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker...
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
15 years 6 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna