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» Synthesis of Operation-Centric Hardware Descriptions
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IPPS
2002
IEEE
15 years 2 months ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...
FPL
2009
Springer
91views Hardware» more  FPL 2009»
15 years 2 months ago
Large multipliers with fewer DSP blocks
Recent computing-oriented FPGAs feature DSP blocks including small embedded multipliers. A large integer multiplier, for instance for a double-precision floating-point multiplier...
Florent de Dinechin, Bogdan Pasca
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
15 years 3 months ago
Scheduling under resource constraints using dis-equations
Scheduling is an important step in high-level synthesis (HLS). In our tool, we perform scheduling in two steps: coarse-grain scheduling, in which we take into account the whole co...
Hadda Cherroun, Alain Darte, Paul Feautrier
ECBS
2002
IEEE
81views Hardware» more  ECBS 2002»
15 years 2 months ago
Optimization of a Retargetable Functional Simulator for Embedded Processors
The objective of this research is to develop tools and methods for system-level optimization of embedded software that is executed on system-on-chip platforms. In particular, this...
Francesco Papariello, Gabriele Luculli
ICCD
2006
IEEE
134views Hardware» more  ICCD 2006»
15 years 3 months ago
Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD
Microfluidics-based biochips offer exciting possibilities for highthroughput sequencing, parallel immunoassays, blood chemistry for clinical diagnostics, DNA sequencing, and envir...
Krishnendu Chakrabarty