127 search results - page 7 / 26 » Synthesis of Operation-Centric Hardware Descriptions |
ICCAD
1998
IEEE
15 years 1 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
ISSS
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
CHARME
2001
Springer
15 years 2 months ago
2001
Springer
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
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ICCAD
1992
IEEE
15 years 1 months ago
1992
IEEE
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
ASPDAC
1995
ACM
15 years 1 months ago
1995
ACM
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto...