Sciweavers

127 search results - page 9 / 26
» Synthesis of Operation-Centric Hardware Descriptions
Sort
View
MSO
2003
14 years 11 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
ACSD
2009
IEEE
106views Hardware» more  ACSD 2009»
14 years 7 months ago
Teak: A Token-Flow Implementation for the Balsa Language
This paper describes a new target component set and synthesis scheme for the Balsa asynchronous hardware description language. This new scheme removes the reliance on precise hands...
Andrew Bardsley, Luis A. Tarazona, Doug A. Edwards
EURODAC
1994
IEEE
221views VHDL» more  EURODAC 1994»
15 years 1 months ago
Implementation of a SDH STM-N IC for B-ISDN using VHDL based synthesis tools
payload. The current recommendations include SDH as the physical layer transmission standard. It is defined the BISDN user network interface (UNI) SDH-based at 155.52 Mbit/s, but t...
Juan Carlos Calderón, Enric Corominas, Jos&...
FPL
2009
Springer
115views Hardware» more  FPL 2009»
15 years 2 months ago
Recursion in reconfigurable computing: A survey of implementation approaches
Reconfigurable systems are widely used nowadays to increase performance of computationally intensive applications. There exist a lot of synthesis tools that automatically generate...
Iouliia Skliarova, Valery Sklyarov
DSD
2010
IEEE
137views Hardware» more  DSD 2010»
14 years 7 months ago
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...