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DAC
2008
ACM
14 years 7 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
DAC
2009
ACM
14 years 7 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
FPGA
2005
ACM
95views FPGA» more  FPGA 2005»
13 years 11 months ago
The Stratix II logic and routing architecture
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...
David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaugh...
BMCBI
2010
150views more  BMCBI 2010»
13 years 6 months ago
AMS 3.0: prediction of post-translational modifications
Background: We present here the recent update of AMS algorithm for identification of post-translational modification (PTM) sites in proteins based only on sequence information, us...
Subhadip Basu, Dariusz Plewczynski
BMCBI
2007
181views more  BMCBI 2007»
13 years 6 months ago
ASMPKS: an analysis system for modular polyketide synthases
Background: Polyketides are secondary metabolites of microorganisms with diverse biological activities, including pharmacological functions such as antibiotic, antitumor and agroc...
Hongseok Tae, Eun-Bae Kong, Kiejung Park