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94
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ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
15 years 10 months ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid
ICES
2010
Springer
277views Hardware» more  ICES 2010»
14 years 11 months ago
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep...
146
Voted
INTEGRATION
2008
183views more  INTEGRATION 2008»
15 years 1 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
CHES
2006
Springer
205views Cryptology» more  CHES 2006»
15 years 5 months ago
Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
Konrad J. Kulikowski, Alexander B. Smirnov, Alexan...
81
Voted
ISLPED
2006
ACM
132views Hardware» more  ISLPED 2006»
15 years 7 months ago
Low-power fanout optimization using MTCMOS and multi-Vt techniques
This paper addresses the problem of low-power fanout optimization. We show that due to neglecting short-circuit current, previous analytical techniques proposed to optimize the ar...
Behnam Amelifard, Farzan Fallah, Massoud Pedram