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» Synthesis of Reversible Logic
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ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
15 years 2 months ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...
64
Voted
MSE
1999
IEEE
118views Hardware» more  MSE 1999»
15 years 1 months ago
Training IP Creators and Integrators
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
Donald W. Bouldin, Senthil Natarajan, Benjamin A. ...
IFM
1999
Springer
15 years 1 months ago
Integration Problems in Telephone Feature Requirements
The feature interaction problem is prominent in telephone service development. Through a number of case studies, we have discovered that no single semantic framework is suitable f...
J. Paul Gibson, Geoff Hamilton, Dominique Mé...
ITC
1996
IEEE
107views Hardware» more  ITC 1996»
15 years 1 months ago
Orthogonal Scan: Low-Overhead Scan for Data Paths
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
Robert B. Norwood, Edward J. McCluskey
DATE
2010
IEEE
130views Hardware» more  DATE 2010»
15 years 1 months ago
Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller
Abstract—Supporting Distributed Shared Memory (DSM) is essential for multi-core Network-on-Chips for the sake of reusing huge amount of legacy code and easy programmability. We p...
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming C...