688 search results - page 134 / 138 » Synthesis of Reversible Logic |
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
FPGA
2010
ACM
15 years 6 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
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CODES
2008
IEEE
15 years 4 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
CASES
2006
ACM
15 years 3 months ago
2006
ACM
Architectural advances of modern systems has often been at odds with control complexity, requiring significant effort in both design and verification. This is particularly true ...