688 search results - page 30 / 138 » Synthesis of Reversible Logic |
AICCSA
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper presents an encoding algorithm that is very efficient for many different logic synthesis problems. The algorithm is based on the use of special tables and includes two ...
ICCAD
2010
IEEE
14 years 7 months ago
2010
IEEE
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
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ICFP
2012
ACM
13 years 4 days ago
2012
ACM
The higher-order logic found in proof assistants such as Coq and various HOL systems provides a convenient setting for the development and verification of pure functional program...
GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...