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» Synthesis of Reversible Logic
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ICCAD
1997
IEEE
142views Hardware» more  ICCAD 1997»
15 years 2 months ago
Library-less synthesis for static CMOS combinational logic circuits
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullel...
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
15 years 3 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
DATE
2010
IEEE
175views Hardware» more  DATE 2010»
15 years 1 months ago
Approximate logic synthesis for error tolerant applications
─ Error tolerance formally captures the notion that – for a wide variety of applications including audio, video, graphics, and wireless communications – a defective chip that...
Doochul Shin, Sandeep K. Gupta
DAC
2005
ACM
15 years 10 months ago
A new canonical form for fast boolean matching in logic synthesis and verification
? An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition an efficient algorithm for co...
Afshin Abdollahi, Massoud Pedram
IPPS
1997
IEEE
15 years 1 months ago
A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis
Algebraic factorization is an extremely important part of any logic synthesis system but is computationally expensive. Hence it is important to look at parallel processing to spee...
Sumit Roy, Prithviraj Banerjee