688 search results - page 49 / 138 » Synthesis of Reversible Logic |
IJCSS
2007
14 years 9 months ago
2007
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
CORR
2010
Springer
14 years 10 months ago
2010
Springer
We introduce a generic extension of the popular branching-time logic CTL which refines the temporal until and release operators with formal languages. For instance, a language may ...
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WCE
2007
14 years 11 months ago
2007
- In the speed-independent logic, the hazards caused by input inverters are identified. The known methods of the elimination of such hazards are based on avoiding input inverters. ...
ITC
1998
IEEE
15 years 2 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...