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» Synthesis of Reversible Logic
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DSD
2010
IEEE
133views Hardware» more  DSD 2010»
14 years 7 months ago
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...
Igor Lemberski, Petr Fiser
DATE
2010
IEEE
119views Hardware» more  DATE 2010»
15 years 2 months ago
Exploiting local logic structures to optimize multi-core SoC floorplanning
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...
Cheng-Hong Li, Sampada Sonalkar, Luca P. Carloni
BANFF
1995
15 years 1 months ago
An Automata-Theoretic Approach to Linear Temporal Logic
The automata-theoretic approach to linear temporal logic uses the theory of automata as a unifying paradigm for program specification, verification, and synthesis. Both programs ...
Moshe Y. Vardi
DAC
2009
ACM
15 years 10 months ago
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
TVLSI
2010
14 years 4 months ago
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
Deming Chen, Jason Cong, Yiping Fan, Lu Wan