688 search results - page 7 / 138 » Synthesis of Reversible Logic |
ASYNC
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
CF
2005
ACM
14 years 11 months ago
2005
ACM
This paper is about making reversible logic a reality for supercomputing. Reversible logic offers a way to exceed certain basic limits on the performance of computers, yet a power...
ICCAD
1998
IEEE
15 years 1 months ago
1998
IEEE
In this paper, we propose a new logic synthesis methodology to deal with the increasing importance of the interconnect delay in deepsubmicron technologies. We first show that conv...
78
Voted
IAJIT
2010
14 years 8 months ago
2010
: In parity preserving reversible circuit, the parity of the input vector must match the parity of the output vector. It renders a wide class of circuit faults readily detectable a...
DAC
2000
ACM
15 years 2 months ago
2000
ACM
In many modern designs, timing is either a key optimization goal and/or a mandatory constraint. We propose the first intellectual property protection technique using watermarking ...