61 search results - page 4 / 13 » Synthesis of Selectively Clocked Skewed Logic Circuits |
DAC
2009
ACM
15 years 4 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
DAC
2008
ACM
14 years 11 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
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ISQED
2008
IEEE
15 years 3 months ago
2008
IEEE
An efficient frequency-based clock analysis method: CSAV is proposed in this paper. It computes the circuit response by first solving the state equation in frequency domain, and...
ASPDAC
2010
ACM
14 years 7 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
ASPDAC
2005
ACM
15 years 3 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...