61 search results - page 5 / 13 » Synthesis of Selectively Clocked Skewed Logic Circuits |
103
Voted
ISQED
2010
IEEE
15 years 4 months ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
DATE
1997
IEEE
15 years 1 months ago
1997
IEEE
A target structure for implementing fast edge-triggered control units is presented. In many cases, the proposed controller is faster than a one-hot encoded structure as its correc...
93
Voted
DAC
2003
ACM
15 years 10 months ago
2003
ACM
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
177
click to vote
DAC
2011
ACM
13 years 9 months ago
2011
ACM
Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...
79
Voted
TVLSI
2010
14 years 4 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...