61 search results - page 7 / 13 » Synthesis of Selectively Clocked Skewed Logic Circuits |
100
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DATE
2000
IEEE
15 years 1 months ago
2000
IEEE
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...
74
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IOLTS
2003
IEEE
15 years 2 months ago
2003
IEEE
A methodology for the synthesis of partially selfchecking multilevel logic circuits with low-cost paritybased concurrent error detection (CED) is described. A subset of the inputs...
93
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ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
108
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DAC
1998
ACM
15 years 1 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
ATS
2000
IEEE
15 years 1 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...