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» Synthesis of Self-Testable Controllers
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DATE
2006
IEEE
108views Hardware» more  DATE 2006»
15 years 8 months ago
Scheduling under resource constraints using dis-equations
Scheduling is an important step in high-level synthesis (HLS). In our tool, we perform scheduling in two steps: coarse-grain scheduling, in which we take into account the whole co...
Hadda Cherroun, Alain Darte, Paul Feautrier
ISCAS
2006
IEEE
92views Hardware» more  ISCAS 2006»
15 years 8 months ago
Time-sliding suboptimal regulation of bilinear interconnected systems
— This paper focuses on the suboptimal regulation of multivariable discrete-time bilinear systems consisting of interconnected bilinear subsystems with respect to a linear quadra...
Manuel de la Sen, Aitor J. Garrido, J. C. Soto, Os...
RSP
2006
IEEE
102views Control Systems» more  RSP 2006»
15 years 8 months ago
Rapid Resource-Constrained Hardware Performance Estimation
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driv...
Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrish...
DATE
2005
IEEE
144views Hardware» more  DATE 2005»
15 years 7 months ago
Context Sensitive Performance Analysis of Automotive Applications
Accurate timing analysis is key to efficient embedded system synthesis and integration. While industrial control software systems are developed using graphical models, such as Ma...
Jan Staschulat, Rolf Ernst, Andreas Schulze, Fabia...
FSTTCS
2005
Springer
15 years 7 months ago
The MSO Theory of Connectedly Communicating Processes
Abstract. We identify a network of sequential processes that communicate by synchronizing frequently on common actions. More precisely, we demand that there is a bound k such that ...
P. Madhusudan, P. S. Thiagarajan, Shaofa Yang