Sciweavers

663 search results - page 116 / 133
» Synthesis of Self-Testable Controllers
Sort
View
CGF
2006
263views more  CGF 2006»
14 years 11 months ago
A Predictive Light Transport Model for the Human Iris
Recently, light interactions with organic matter have become the object of detailed investigations by image synthesis researchers. Besides allowing these materials to be rendered ...
Michael W. Y. Lam, Gladimir V. G. Baranoski
DAC
2003
ACM
16 years 20 days ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
DAC
2003
ACM
16 years 20 days ago
Data communication estimation and reduction for reconfigurable systems
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
Adam Kaplan, Philip Brisk, Ryan Kastner
97
Voted
DAC
2006
ACM
16 years 20 days ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
VLSID
2007
IEEE
231views VLSI» more  VLSID 2007»
16 years 2 days ago
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Ma...