663 search results - page 65 / 133 » Synthesis of Self-Testable Controllers |
193
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RSP
2005
IEEE
16 years 8 days ago
2005
IEEE
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
183
Voted
ISSS
2002
IEEE
15 years 11 months ago
2002
IEEE
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
174
Voted
ASPDAC
1995
ACM
15 years 10 months ago
1995
ACM
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
145
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MEMOCODE
2005
IEEE
16 years 8 days ago
2005
IEEE
The SystemVerilog standard introduces SystemVerilog Assertions (SVA), a synchronous assertion package based on the temporal-logic semantics of PSL. Traditionally assertions are ch...
158
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
— This paper introduces the concept of kl-feasible cuts, by controlling both the number k of inputs and the number l of outputs in a circuit cut. To provide scalability, the conc...