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» Synthesis of Self-Testable Controllers
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123
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ASPDAC
1995
ACM
127views Hardware» more  ASPDAC 1995»
15 years 6 months ago
Reclocking for high-level synthesis
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...
Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran
104
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AMC
2007
91views more  AMC 2007»
15 years 2 months ago
Deterministic and random synthesis of discrete chaos
In this paper, two anticontrol algorithms for synthesis of discrete chaos are introduced. In these algorithms, the control parameter of a discrete dynamical system is switched, ei...
Miguel Romera, Michael Small, Marius-F. Danca
151
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INTEGRATION
2006
102views more  INTEGRATION 2006»
15 years 2 months ago
A parameterized graph-based framework for high-level test synthesis
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilz...
117
Voted
ICASSP
2009
IEEE
15 years 9 months ago
Pitch bends and tonguing articulation in clarinet physical modeling synthesis
A physical modeling approach is used to investigate playing effects in woodwind instruments. This builds upon prior work concerning both empirical studies of the acoustics of the ...
Mark Sterling, Xiaoxiao Dong, Mark Bocko
153
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FDL
2007
IEEE
15 years 9 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton