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» Synthesis of Self-Testable Controllers
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CODES
2006
IEEE
15 years 8 months ago
Thermal-aware high-level synthesis based on network flow method
Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reli...
Pilok Lim, Taewhan Kim
114
Voted
ISCAS
2005
IEEE
144views Hardware» more  ISCAS 2005»
15 years 8 months ago
Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis
— Multicycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the...
M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter K...
96
Voted
DATE
2010
IEEE
140views Hardware» more  DATE 2010»
15 years 7 months ago
Construction of dual mode components for reconfiguration aware high-level synthesis
High-level synthesis has recently started to gain industrial acceptance, due to the improved quality of results and the multi-objective optimizations offered. One optimization area...
George Economakos, Sotirios Xydis, Ioannis Koutras...
129
Voted
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
15 years 7 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr
108
Voted
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
15 years 6 months ago
A general state graph transformation framework for asynchronous synthesis
Abstract -- A general framework for synthesis of asynchronous control circuits at the state graph level is proposed. The framework can consider both concurrency reduction as well a...
Bill Lin, Chantal Ykman-Couvreur, Peter Vanbekberg...