663 search results - page 91 / 133 » Synthesis of Self-Testable Controllers |
165
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
153
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ICARCV
2008
IEEE
16 years 26 days ago
2008
IEEE
—In this paper, we study the problem of stabilizing a linear time-invariant discrete-time system with information constraints in the input channels. The information constraint in...
156
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ICCAD
2007
IEEE
16 years 22 days ago
2007
IEEE
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
221
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CODES
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...
156
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ISSS
2002
IEEE
15 years 11 months ago
2002
IEEE
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...